Dr.T. Nandha Kumar received his Bachelor and Master degrees from University of Madras and National Institute of Technology, India respectively. Subsequently he obtained Ph.D. in Electrical and Electronic Engineering from The University of Nottingham. Currently he is working as an associate professor at The University of Nottingham, Malaysia. Prior to this, he was working at Intel Corporation as a senior pre-silicon validation engineer and involved in the gate level validation of IO chips ICH4 and ICH5. He also worked as the gate level validation lead for ICH6 IO chip and RTL validation lead for legacy units of ICH7 and ICH8 IO chip.
Dr.Nandha has 15 years of academic and 5 years of Industrial experience. His research interests are in the field of VLSI design, Test, fault/defect tolerance of digital systems, Nano electronics, Emerging Non-volatile memory and Approximate Computing. He has published more than 70 papers in the reputed International journals and conferences. His team's work on NV memory has been selected by Institute of Physics (IOP) "Semiconductor Science and Technology" as one of the HIGHLIGHTS of 2015. Also his team's work on approximate computing has been nominated for BEST PAPER AWARD in DATE 2016.
He serves as an Associate Editor of IET Circuits, Devices and Systems, reviewer for IEEE Transaction on Nanotechnology, IEEE Transactions on Emerging Topics in Computational Intelligence, IET Journal of Engineering, Elsevier Microprocessor and Microsystems, Elsevier Microelectronics, Elsevier Measurement. Also he served as a technical committee member for more than 70 IEEE international conferences.
Dr.Nandha is a Fellow of Higher Education Academy (UK), Charted Engineer (UK), Senior member IEEE, Member IET and Member TRIZ association.
1. VLSI Design (H63VLSI) - Spring
2. HDL for Programmable Logic (H64HPL) - Autumn
3. HDL for Programmable Logic with project (H64HPP) - Year Long
Research interests and projects:
- Emerging Non-Volatile Memory
- Nano Electronics
- Approximate Computing
- Reliability testing of reconfigurable integrated circuits such as field programmable gate arrays (FPGA).
- VLSI Design
- Hardware realization - FPGA Based
T. NANDHA KUMAR, HAIDER ABBAS F ALMURIB and FABRIZIO LOMBARDI, 2013. Single-configuration fault detection in application-dependent testing of field programmable gate array interconnects IET Transactions on Computers & Digital Techniques. 7(3), 132-141 HAIDER AF ALMURIB,, T NANDHA KUMAR and FABRIZIO LOMBARDI, 2014. Scalable Application-Dependent Diagnosis of Interconnects of SRAM-based FPGAs IEEE Transactions on Computers. T. NANDHA KUMAR, HAIDER A. F. ALMURIB and NEW CHIN-EE, 2012. Fine Grain Faults Diagnosis of FPGA Interconnect Journal of Microprocessors and Microsystems. 31(1), 33-40
WENYI FENG, FABRIZIO LOMBARDI, HAIDER AF ALMURIB and T. NANDHA KUMAR, 2013. Testing a Nano Crossbar for Multiple Fault Detection IEEE Transactions on Nano Technology. 12(4), 477 - 485
1. Director of Research E & E Eng
2. Electronic Strand Leader
3. Admissions Tutor E & E Eng